axplat_aarch64_peripherals/
generic_timer.rs1use aarch64_cpu::registers::{CNTFRQ_EL0, CNTP_CTL_EL0, CNTP_TVAL_EL0, CNTPCT_EL0};
4use aarch64_cpu::registers::{Readable, Writeable};
5use int_ratio::Ratio;
6
7static mut CNTPCT_TO_NANOS_RATIO: Ratio = Ratio::zero();
8static mut NANOS_TO_CNTPCT_RATIO: Ratio = Ratio::zero();
9
10#[inline]
12pub fn current_ticks() -> u64 {
13 CNTPCT_EL0.get()
14}
15
16#[inline]
18pub fn ticks_to_nanos(ticks: u64) -> u64 {
19 unsafe { CNTPCT_TO_NANOS_RATIO.mul_trunc(ticks) }
20}
21
22#[inline]
24pub fn nanos_to_ticks(nanos: u64) -> u64 {
25 unsafe { NANOS_TO_CNTPCT_RATIO.mul_trunc(nanos) }
26}
27
28pub fn set_oneshot_timer(deadline_ns: u64) {
32 let cnptct = CNTPCT_EL0.get();
33 let cnptct_deadline = nanos_to_ticks(deadline_ns);
34 if cnptct < cnptct_deadline {
35 let interval = cnptct_deadline - cnptct;
36 debug_assert!(interval <= u32::MAX as u64);
37 CNTP_TVAL_EL0.set(interval);
38 } else {
39 CNTP_TVAL_EL0.set(0);
40 }
41}
42
43pub fn init_early() {
45 let freq = CNTFRQ_EL0.get();
46 unsafe {
47 CNTPCT_TO_NANOS_RATIO = Ratio::new(axplat::time::NANOS_PER_SEC as u32, freq as u32);
48 NANOS_TO_CNTPCT_RATIO = CNTPCT_TO_NANOS_RATIO.inverse();
49 }
50}
51
52pub fn enable_irqs(timer_irq_num: usize) {
57 CNTP_CTL_EL0.write(CNTP_CTL_EL0::ENABLE::SET);
58 CNTP_TVAL_EL0.set(0);
59 crate::gic::set_enable(timer_irq_num, true);
60}
61
62#[macro_export]
65macro_rules! time_if_impl {
66 ($name:ident) => {
67 struct $name;
68
69 #[impl_plat_interface]
70 impl axplat::time::TimeIf for $name {
71 fn current_ticks() -> u64 {
73 $crate::generic_timer::current_ticks()
74 }
75
76 fn ticks_to_nanos(ticks: u64) -> u64 {
78 $crate::generic_timer::ticks_to_nanos(ticks)
79 }
80
81 fn nanos_to_ticks(nanos: u64) -> u64 {
83 $crate::generic_timer::nanos_to_ticks(nanos)
84 }
85
86 fn epochoffset_nanos() -> u64 {
89 $crate::pl031::epochoffset_nanos()
90 }
91
92 fn set_oneshot_timer(deadline_ns: u64) {
97 $crate::generic_timer::set_oneshot_timer(deadline_ns)
98 }
99 }
100 };
101}