axhal/
paging.rs

1//! Page table manipulation.
2
3use axalloc::global_allocator;
4use memory_addr::{PAGE_SIZE_4K, PhysAddr, VirtAddr};
5use page_table_multiarch::PagingHandler;
6
7use crate::mem::{phys_to_virt, virt_to_phys};
8
9#[doc(no_inline)]
10pub use page_table_multiarch::{MappingFlags, PageSize, PagingError, PagingResult};
11
12/// Implementation of [`PagingHandler`], to provide physical memory manipulation to
13/// the [page_table_multiarch] crate.
14pub struct PagingHandlerImpl;
15
16impl PagingHandler for PagingHandlerImpl {
17    fn alloc_frame() -> Option<PhysAddr> {
18        global_allocator()
19            .alloc_pages(1, PAGE_SIZE_4K)
20            .map(|vaddr| virt_to_phys(vaddr.into()))
21            .ok()
22    }
23
24    fn dealloc_frame(paddr: PhysAddr) {
25        global_allocator().dealloc_pages(phys_to_virt(paddr).as_usize(), 1)
26    }
27
28    #[inline]
29    fn phys_to_virt(paddr: PhysAddr) -> VirtAddr {
30        phys_to_virt(paddr)
31    }
32}
33
34cfg_if::cfg_if! {
35    if #[cfg(target_arch = "x86_64")] {
36        /// The architecture-specific page table.
37        pub type PageTable = page_table_multiarch::x86_64::X64PageTable<PagingHandlerImpl>;
38    } else if #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] {
39        /// The architecture-specific page table.
40        pub type PageTable = page_table_multiarch::riscv::Sv39PageTable<PagingHandlerImpl>;
41    } else if #[cfg(target_arch = "aarch64")]{
42        /// The architecture-specific page table.
43        pub type PageTable = page_table_multiarch::aarch64::A64PageTable<PagingHandlerImpl>;
44    } else if #[cfg(target_arch = "loongarch64")] {
45        /// The architecture-specific page table.
46        pub type PageTable = page_table_multiarch::loongarch64::LA64PageTable<PagingHandlerImpl>;
47    }
48}
axhal/paging.rs

axhal/
paging.rs
