axhal/
paging.rs

1//! Page table manipulation.
2
3use axalloc::global_allocator;
4use lazyinit::LazyInit;
5use page_table_multiarch::PagingHandler;
6
7use crate::mem::{MemRegionFlags, PAGE_SIZE_4K, PhysAddr, VirtAddr, phys_to_virt, virt_to_phys};
8
9#[doc(no_inline)]
10pub use page_table_multiarch::{MappingFlags, PageSize, PagingError, PagingResult};
11
12impl From<MemRegionFlags> for MappingFlags {
13    fn from(f: MemRegionFlags) -> Self {
14        let mut ret = Self::empty();
15        if f.contains(MemRegionFlags::READ) {
16            ret |= Self::READ;
17        }
18        if f.contains(MemRegionFlags::WRITE) {
19            ret |= Self::WRITE;
20        }
21        if f.contains(MemRegionFlags::EXECUTE) {
22            ret |= Self::EXECUTE;
23        }
24        if f.contains(MemRegionFlags::DEVICE) {
25            ret |= Self::DEVICE;
26        }
27        if f.contains(MemRegionFlags::UNCACHED) {
28            ret |= Self::UNCACHED;
29        }
30        ret
31    }
32}
33
34/// Implementation of [`PagingHandler`], to provide physical memory manipulation to
35/// the [page_table_multiarch] crate.
36pub struct PagingHandlerImpl;
37
38impl PagingHandler for PagingHandlerImpl {
39    fn alloc_frame() -> Option<PhysAddr> {
40        global_allocator()
41            .alloc_pages(1, PAGE_SIZE_4K)
42            .map(|vaddr| virt_to_phys(vaddr.into()))
43            .ok()
44    }
45
46    fn dealloc_frame(paddr: PhysAddr) {
47        global_allocator().dealloc_pages(phys_to_virt(paddr).as_usize(), 1)
48    }
49
50    #[inline]
51    fn phys_to_virt(paddr: PhysAddr) -> VirtAddr {
52        phys_to_virt(paddr)
53    }
54}
55
56cfg_if::cfg_if! {
57    if #[cfg(target_arch = "x86_64")] {
58        /// The architecture-specific page table.
59        pub type PageTable = page_table_multiarch::x86_64::X64PageTable<PagingHandlerImpl>;
60    } else if #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] {
61        /// The architecture-specific page table.
62        pub type PageTable = page_table_multiarch::riscv::Sv39PageTable<PagingHandlerImpl>;
63    } else if #[cfg(target_arch = "aarch64")]{
64        /// The architecture-specific page table.
65        pub type PageTable = page_table_multiarch::aarch64::A64PageTable<PagingHandlerImpl>;
66    } else if #[cfg(target_arch = "loongarch64")] {
67        /// The architecture-specific page table.
68        pub type PageTable = page_table_multiarch::loongarch64::LA64PageTable<PagingHandlerImpl>;
69    }
70}
71
72static KERNEL_PAGE_TABLE_ROOT: LazyInit<PhysAddr> = LazyInit::new();
73
74/// Saves the root physical address of the kernel page table, which may be used
75/// on context switch.
76pub fn set_kernel_page_table_root(root_paddr: PhysAddr) {
77    KERNEL_PAGE_TABLE_ROOT.call_once(|| root_paddr);
78    unsafe { crate::arch::write_page_table_root(root_paddr) };
79}
80
81/// Get the root physical address of the kernel page table.
82///
83/// # Panics
84///
85/// It must be called after [`set_kernel_page_table_root`], otherwise it will panic.
86pub fn kernel_page_table_root() -> PhysAddr {
87    *KERNEL_PAGE_TABLE_ROOT
88        .get()
89        .expect("kernel page table not initialized")
90}
axhal/paging.rs

axhal/
paging.rs
