1use core::ffi::c_int;
2
3use crate::ctypes;
4
5#[unsafe(naked)]
7#[unsafe(no_mangle)]
8pub unsafe extern "C" fn setjmp(_buf: *mut ctypes::__jmp_buf_tag) {
9 #[cfg(all(target_arch = "aarch64", feature = "fp-simd"))]
10 core::arch::naked_asm!(
11 ".arch armv8
12 stp x19, x20, [x0,#0]
13 stp x21, x22, [x0,#16]
14 stp x23, x24, [x0,#32]
15 stp x25, x26, [x0,#48]
16 stp x27, x28, [x0,#64]
17 stp x29, x30, [x0,#80]
18 mov x2, sp
19 str x2, [x0,#104]
20 stp d8, d9, [x0,#112]
21 stp d10, d11, [x0,#128]
22 stp d12, d13, [x0,#144]
23 stp d14, d15, [x0,#160]
24 mov x0, #0
25 ret",
26 );
27 #[cfg(all(target_arch = "aarch64", not(feature = "fp-simd")))]
28 core::arch::naked_asm!(
29 "
30 stp x19, x20, [x0,#0]
31 stp x21, x22, [x0,#16]
32 stp x23, x24, [x0,#32]
33 stp x25, x26, [x0,#48]
34 stp x27, x28, [x0,#64]
35 stp x29, x30, [x0,#80]
36 mov x2, sp
37 str x2, [x0,#104]
38 mov x0, #0
39 ret",
40 );
41 #[cfg(target_arch = "x86_64")]
42 core::arch::naked_asm!(
43 "mov [rdi], rbx
44 mov [rdi + 8], rbp
45 mov [rdi + 16], r12
46 mov [rdi + 24], r13
47 mov [rdi + 32], r14
48 mov [rdi + 40], r15
49 lea rdx, [rsp + 8]
50 mov [rdi + 48], rdx
51 mov rdx, [rsp]
52 mov [rdi + 56], rdx
53 xor rax, rax
54 ret",
55 );
56 #[cfg(all(target_arch = "riscv64", feature = "fp-simd"))]
57 core::arch::naked_asm!(
58 "sd s0, 0(a0)
59 sd s1, 8(a0)
60 sd s2, 16(a0)
61 sd s3, 24(a0)
62 sd s4, 32(a0)
63 sd s5, 40(a0)
64 sd s6, 48(a0)
65 sd s7, 56(a0)
66 sd s8, 64(a0)
67 sd s9, 72(a0)
68 sd s10, 80(a0)
69 sd s11, 88(a0)
70 sd sp, 96(a0)
71 sd ra, 104(a0)
72
73 fsd fs0, 112(a0)
74 fsd fs1, 120(a0)
75 fsd fs2, 128(a0)
76 fsd fs3, 136(a0)
77 fsd fs4, 144(a0)
78 fsd fs5, 152(a0)
79 fsd fs6, 160(a0)
80 fsd fs7, 168(a0)
81 fsd fs8, 176(a0)
82 fsd fs9, 184(a0)
83 fsd fs10, 192(a0)
84 fsd fs11, 200(a0)
85
86 li a0, 0
87 ret",
88 );
89 #[cfg(all(target_arch = "riscv64", not(feature = "fp-simd")))]
90 core::arch::naked_asm!(
91 "sd s0, 0(a0)
92 sd s1, 8(a0)
93 sd s2, 16(a0)
94 sd s3, 24(a0)
95 sd s4, 32(a0)
96 sd s5, 40(a0)
97 sd s6, 48(a0)
98 sd s7, 56(a0)
99 sd s8, 64(a0)
100 sd s9, 72(a0)
101 sd s10, 80(a0)
102 sd s11, 88(a0)
103 sd sp, 96(a0)
104 sd ra, 104(a0)
105
106 li a0, 0
107 ret",
108 );
109 #[cfg(all(target_arch = "loongarch64", feature = "fp-simd"))]
110 core::arch::naked_asm!(
111 "
112 st.d $ra, $a0, 0
113 st.d $sp, $a0, 1 * 8
114 st.d $s0, $a0, 2 * 8
115 st.d $s1, $a0, 3 * 8
116 st.d $s2, $a0, 4 * 8
117 st.d $s3, $a0, 5 * 8
118 st.d $s4, $a0, 6 * 8
119 st.d $s5, $a0, 7 * 8
120 st.d $s6, $a0, 8 * 8
121 st.d $s7, $a0, 9 * 8
122 st.d $s8, $a0, 10 * 8
123 st.d $fp, $a0, 11 * 8
124 st.d $r1, $a0, 12 * 8
125 fst.d $f24, $a0, 13 * 8
126 fst.d $f25, $a0, 14 * 8
127 fst.d $f26, $a0, 15 * 8
128 fst.d $f27, $a0, 16 * 8
129 fst.d $f28, $a0, 17 * 8
130 fst.d $f29, $a0, 18 * 8
131 fst.d $f30, $a0, 19 * 8
132 fst.d $f31, $a0, 20 * 8
133 li.w $a0, 0
134 ret",
135 );
136 #[cfg(all(target_arch = "loongarch64", not(feature = "fp-simd")))]
137 core::arch::naked_asm!(
138 "
139 st.d $ra, $a0, 0
140 st.d $sp, $a0, 1 * 8
141 st.d $s0, $a0, 2 * 8
142 st.d $s1, $a0, 3 * 8
143 st.d $s2, $a0, 4 * 8
144 st.d $s3, $a0, 5 * 8
145 st.d $s4, $a0, 6 * 8
146 st.d $s5, $a0, 7 * 8
147 st.d $s6, $a0, 8 * 8
148 st.d $s7, $a0, 9 * 8
149 st.d $s8, $a0, 10 * 8
150 st.d $fp, $a0, 11 * 8
151 st.d $r1, $a0, 12 * 8
152 li.w $a0, 0
153 ret",
154 );
155 #[cfg(all(target_arch = "arm", feature = "fp-simd"))]
156 core::arch::naked_asm!(
157 "str r4, [r0, #0]
158 str r5, [r0, #4]
159 str r6, [r0, #8]
160 str r7, [r0, #12]
161 str r8, [r0, #16]
162 str r9, [r0, #20]
163 str r10, [r0, #24]
164 str r11, [r0, #28]
165 str sp, [r0, #32]
166 str lr, [r0, #36]
167 vstr d8, [r0, #40]
168 vstr d9, [r0, #48]
169 vstr d10, [r0, #56]
170 vstr d11, [r0, #64]
171 vstr d12, [r0, #72]
172 vstr d13, [r0, #80]
173 vstr d14, [r0, #88]
174 vstr d15, [r0, #96]
175 mov r0, #0
176 bx lr",
177 );
178
179 #[cfg(all(target_arch = "arm", not(feature = "fp-simd")))]
180 core::arch::naked_asm!(
181 "str r4, [r0, #0]
182 str r5, [r0, #4]
183 str r6, [r0, #8]
184 str r7, [r0, #12]
185 str r8, [r0, #16]
186 str r9, [r0, #20]
187 str r10, [r0, #24]
188 str r11, [r0, #28]
189 str sp, [r0, #32]
190 str lr, [r0, #36]
191 mov r0, #0
192 bx lr",
193 );
194
195 #[cfg(not(any(
196 target_arch = "aarch64",
197 target_arch = "x86_64",
198 target_arch = "riscv64",
199 target_arch = "loongarch64",
200 target_arch = "arm"
201 )))]
202 compile_error!("Unsupported target architecture for setjmp");
203}
204
205#[unsafe(naked)]
207#[unsafe(no_mangle)]
208pub unsafe extern "C" fn longjmp(_buf: *mut ctypes::__jmp_buf_tag, _val: c_int) -> ! {
209 #[cfg(all(target_arch = "aarch64", feature = "fp-simd"))]
210 core::arch::naked_asm!(
211 ".arch armv8
212 ldp x19, x20, [x0,#0]
213 ldp x21, x22, [x0,#16]
214 ldp x23, x24, [x0,#32]
215 ldp x25, x26, [x0,#48]
216 ldp x27, x28, [x0,#64]
217 ldp x29, x30, [x0,#80]
218 ldr x2, [x0,#104]
219 mov sp, x2
220 ldp d8 , d9, [x0,#112]
221 ldp d10, d11, [x0,#128]
222 ldp d12, d13, [x0,#144]
223 ldp d14, d15, [x0,#160]
224
225 cmp w1, 0
226 csinc w0, w1, wzr, ne
227 br x30",
228 );
229 #[cfg(all(target_arch = "aarch64", not(feature = "fp-simd")))]
230 core::arch::naked_asm!(
231 "ldp x19, x20, [x0,#0]
232 ldp x21, x22, [x0,#16]
233 ldp x23, x24, [x0,#32]
234 ldp x25, x26, [x0,#48]
235 ldp x27, x28, [x0,#64]
236 ldp x29, x30, [x0,#80]
237 ldr x2, [x0,#104]
238 mov sp, x2
239
240 cmp w1, 0
241 csinc w0, w1, wzr, ne
242 br x30",
243 );
244 #[cfg(target_arch = "x86_64")]
245 core::arch::naked_asm!(
246 "mov rax,rsi
247 test rax,rax
248 jnz 2f
249 inc rax
250 2:
251 mov rbx, [rdi]
252 mov rbp, [rdi + 8]
253 mov r12, [rdi + 16]
254 mov r13, [rdi + 24]
255 mov r14, [rdi + 32]
256 mov r15, [rdi + 40]
257 mov rdx, [rdi + 48]
258 mov rsp, rdx
259 mov rdx, [rdi + 56]
260 jmp rdx",
261 );
262 #[cfg(all(target_arch = "riscv64", feature = "fp-simd"))]
263 core::arch::naked_asm!(
264 "ld s0, 0(a0)
265 ld s1, 8(a0)
266 ld s2, 16(a0)
267 ld s3, 24(a0)
268 ld s4, 32(a0)
269 ld s5, 40(a0)
270 ld s6, 48(a0)
271 ld s7, 56(a0)
272 ld s8, 64(a0)
273 ld s9, 72(a0)
274 ld s10, 80(a0)
275 ld s11, 88(a0)
276 ld sp, 96(a0)
277 ld ra, 104(a0)
278
279 fld fs0, 112(a0)
280 fld fs1, 120(a0)
281 fld fs2, 128(a0)
282 fld fs3, 136(a0)
283 fld fs4, 144(a0)
284 fld fs5, 152(a0)
285 fld fs6, 160(a0)
286 fld fs7, 168(a0)
287 fld fs8, 176(a0)
288 fld fs9, 184(a0)
289 fld fs10, 192(a0)
290 fld fs11, 200(a0)
291
292 seqz a0, a1
293 add a0, a0, a1
294 ret",
295 );
296 #[cfg(all(target_arch = "riscv64", not(feature = "fp-simd")))]
297 core::arch::naked_asm!(
298 "ld s0, 0(a0)
299 ld s1, 8(a0)
300 ld s2, 16(a0)
301 ld s3, 24(a0)
302 ld s4, 32(a0)
303 ld s5, 40(a0)
304 ld s6, 48(a0)
305 ld s7, 56(a0)
306 ld s8, 64(a0)
307 ld s9, 72(a0)
308 ld s10, 80(a0)
309 ld s11, 88(a0)
310 ld sp, 96(a0)
311 ld ra, 104(a0)
312
313 seqz a0, a1
314 add a0, a0, a1
315 ret",
316 );
317
318 #[cfg(all(target_arch = "loongarch64", feature = "fp-simd"))]
319 core::arch::naked_asm!(
320 "
321 ld.d $ra, $a1, 0
322 ld.d $s0, $a1, 2 * 8
323 ld.d $s1, $a1, 3 * 8
324 ld.d $s2, $a1, 4 * 8
325 ld.d $s3, $a1, 5 * 8
326 ld.d $s4, $a1, 6 * 8
327 ld.d $s5, $a1, 7 * 8
328 ld.d $s6, $a1, 8 * 8
329 ld.d $s7, $a1, 9 * 8
330 ld.d $s8, $a1, 10 * 8
331 ld.d $fp, $a1, 11 * 8
332 ld.d $sp, $a1, 1 * 8
333 ld.d $r21, $a1, 12 * 8
334 fld.d $f24, $a0, 13 * 8
335 fld.d $f25, $a0, 14 * 8
336 fld.d $f26, $a0, 15 * 8
337 fld.d $f27, $a0, 16 * 8
338 fld.d $f28, $a0, 17 * 8
339 fld.d $f29, $a0, 18 * 8
340 fld.d $f30, $a0, 19 * 8
341 fld.d $f31, $a0, 20 * 8
342 sltui $a0, $a1, 1
343 add.d $a0, $a0, $a1
344 jirl $zero,$ra, 0"
345 );
346 #[cfg(all(target_arch = "loongarch64", not(feature = "fp-simd")))]
347 core::arch::naked_asm!(
348 "
349 ld.d $ra, $a1, 0
350 ld.d $s0, $a1, 2 * 8
351 ld.d $s1, $a1, 3 * 8
352 ld.d $s2, $a1, 4 * 8
353 ld.d $s3, $a1, 5 * 8
354 ld.d $s4, $a1, 6 * 8
355 ld.d $s5, $a1, 7 * 8
356 ld.d $s6, $a1, 8 * 8
357 ld.d $s7, $a1, 9 * 8
358 ld.d $s8, $a1, 10 * 8
359 ld.d $fp, $a1, 11 * 8
360 ld.d $sp, $a1, 1 * 8
361 ld.d $r21, $a1, 12 * 8
362 sltui $a0, $a1, 1
363 add.d $a0, $a0, $a1
364 jirl $zero,$ra, 0",
365 );
366 #[cfg(all(target_arch = "arm", feature = "fp-simd"))]
367 core::arch::naked_asm!(
368 "ldr r4, [r0, #0]
369 ldr r5, [r0, #4]
370 ldr r6, [r0, #8]
371 ldr r7, [r0, #12]
372 ldr r8, [r0, #16]
373 ldr r9, [r0, #20]
374 ldr r10, [r0, #24]
375 ldr r11, [r0, #28]
376 ldr sp, [r0, #32]
377 ldr lr, [r0, #36]
378 vldr d8, [r0, #40]
379 vldr d9, [r0, #48]
380 vldr d10, [r0, #56]
381 vldr d11, [r0, #64]
382 vldr d12, [r0, #72]
383 vldr d13, [r0, #80]
384 vldr d14, [r0, #88]
385 vldr d15, [r0, #96]
386 cmp r1, #0
387 moveq r0, #1
388 movne r0, r1
389 bx lr",
390 );
391
392 #[cfg(all(target_arch = "arm", not(feature = "fp-simd")))]
393 core::arch::naked_asm!(
394 "ldr r4, [r0, #0]
395 ldr r5, [r0, #4]
396 ldr r6, [r0, #8]
397 ldr r7, [r0, #12]
398 ldr r8, [r0, #16]
399 ldr r9, [r0, #20]
400 ldr r10, [r0, #24]
401 ldr r11, [r0, #28]
402 ldr sp, [r0, #32]
403 ldr lr, [r0, #36]
404 cmp r1, #0
405 moveq r0, #1
406 movne r0, r1
407 bx lr",
408 );
409
410 #[cfg(not(any(
411 target_arch = "aarch64",
412 target_arch = "x86_64",
413 target_arch = "riscv64",
414 target_arch = "loongarch64",
415 target_arch = "arm"
416 )))]
417 compile_error!("Unsupported target architecture for longjmp");
418}