axmm/backend/
linear.rs

1use axhal::paging::{MappingFlags, PageTable};
2use memory_addr::{PhysAddr, VirtAddr};
3
4use super::Backend;
5
6impl Backend {
7    /// Creates a new linear mapping backend.
8    pub const fn new_linear(pa_va_offset: usize) -> Self {
9        Self::Linear { pa_va_offset }
10    }
11
12    pub(crate) fn map_linear(
13        &self,
14        start: VirtAddr,
15        size: usize,
16        flags: MappingFlags,
17        pt: &mut PageTable,
18        pa_va_offset: usize,
19    ) -> bool {
20        let va_to_pa = |va: VirtAddr| PhysAddr::from(va.as_usize() - pa_va_offset);
21        debug!(
22            "map_linear: [{:#x}, {:#x}) -> [{:#x}, {:#x}) {:?}",
23            start,
24            start + size,
25            va_to_pa(start),
26            va_to_pa(start + size),
27            flags
28        );
29        pt.map_region(start, va_to_pa, size, flags, false, false)
30            .map(|tlb| tlb.ignore()) // TLB flush on map is unnecessary, as there are no outdated mappings.
31            .is_ok()
32    }
33
34    pub(crate) fn unmap_linear(
35        &self,
36        start: VirtAddr,
37        size: usize,
38        pt: &mut PageTable,
39        _pa_va_offset: usize,
40    ) -> bool {
41        debug!("unmap_linear: [{:#x}, {:#x})", start, start + size);
42        pt.unmap_region(start, size, true)
43            .map(|tlb| tlb.ignore()) // flush each page on unmap, do not flush the entire TLB.
44            .is_ok()
45    }
46}
axmm/backend/linear.rs

axmm/backend/
linear.rs
